Field of the Invention:
The invention relates to an electrical component, particularly an integrated semiconductor circuit with a contact, and a method for constructing a contact.
Semiconductor components typically contain integrated circuits that are produced by surface structuring on a semiconductor material, such as silicon or binary, tertiary or quaternary compound semiconductors, as well as contact configurations. The semiconductor material is provided in the form of thin wafers. Progressive miniaturization, whereby structure widths of less than a micrometer (sub-xcexcm) are currently being realized, makes it possible to fabricate a plurality of integrated circuits on one wafer.
At the end of the process of fabricating the integrated circuits, the wafers are divided into individual integrated circuits and/or groups thereof. These are then packaged in electrically insulating housings and are electrically drivable by way of external contacts that are provided on the housings.
For semiconductor components, functionality tests are typically performed even during the production process after each individual step and/or after a defined number of steps. Test analyses are carried out particularly after complicated steps or after steps which experience has shown to be highly susceptible to error.
In the typical functionality tests on individual structural elements or individually deposited layers such as dopant layers, metallization layers or isolating oxide layers, electrical parameters such as voltage or current are usually measured. Comprehensive testing of the functionality of the overall circuit is also frequently carried out during the fabrication process. For testing purposes, individual memory cells of the chip may be activated and tested.
In the test operation, contact pins in the form of test pins are generally placed on the contact surfaces (pads). The test pins are connected to external probe devices or control devices with which the current-voltage dependencies which are required by the integrated circuit in the respective state of processing, or capacities of individual components such as transistors or capacitors, are tested.
Owing to the complexity of the circuit configurations, individual contact pins or test pins are not utilized for this purpose; rather, a multi-pin card in the form of a test board is utilized. In the pin card, the pin spacing is selected according to the spacing of the pads of the integrated circuit that are to be contacted.
The multiplicity of the pads that are to be contacted for test purposes, but more so their small size, demand high precision in the placement of the test pins of a multi-pin card on the surface of the semiconductor material. Successful placement of the test pins for purposes of executing a functionality test may require several passes in order to be able to guarantee the positional precision, which is time-consuming. Besides this, the tips of the pins can become slightly deformed in the placement of the test pins on the pads. As a result, the desired contact of the test pin and the pad may not exist, and on the other hand, it may be impossible to use the deformed pin for further functionality tests, so that it must be replaced.
In addition, during placement, the point of a test pin can slide beyond the edge of the pad and destroy the neighboring layers on the semiconductor surface. A pin can destroy an electrically insulating oxide layer and thus produce unwanted electrical contact. A passivation layer or other layer such as an insulating varnish layer can also be harmed by the point of a pin that has been incorrectly set on a pad. That can have long-term effects besides immediately impairing the electrical characteristics. For instance, moisture can penetrate the integrated circuit through a tear in an insulating layer that has been caused by the pin, causing the integrated circuit to no longer function according to requirements.
Heretofore, such disadvantageous damage has been detected by photo-optical examination. By photo-optical examination, damage at the margin of the pad, known as pad edge damage, can only be detected at the end of the fabrication process, and consequently the entire wafer has to be discarded when damage is discovered. In particular, with conventional photo-optical examinations, it is impossible to preventively detect pin deformations or off-center contact before they lead to surface damage.
Japanese Patent Abstract JP 09-107011a describes an aligning pad in which a central pad is surrounded by a segmented conductive edge strip, whereby all parts of the pad are grounded to a different resistance. By measuring the current, it can then be determined which part of the contact pad an alignment probe sits on.
It is accordingly an object of the invention to provide an electrical component with a contact and a method for forming a contact on a semiconductor material that overcomes the above-mentioned disadvantages of the prior art devices of this general type, on which misalignments or deformations of contact elements which occur in a functionality test can be detected easily and directly without additional analytical devices.
With the foregoing and other objects in view there is provided, in accordance with the invention, an electrical component. The electrical component contains at least one pad formed of an electrically conductive material for receiving an application of a contact element being a test pin. The pad is configured for the application of the test pin for function tests and/or for fastening a connecting wire to the pad. An electrically conductive edge strip is disposed in a region of the pad and has a terminal. The electrically conductive edge strip is electrically isolated from the pad. Evaluation logic for detecting an electrical short is connected to the terminal.
One or more pads are provided on the inventive electrical component, which is formed of an electrically conductive material and which serves for the placement of contact elements. According to the invention, each of the pads contains an electrically conductive edge strip that is isolated from the pads. The advantage herein is that misalignment or deformation of contact elements is indicated by way of an electrical contact of the edge strip and the pad.
In the context of the invention, an electrical component is, above all else, a semiconductor element on which integrated circuits are provided, which circuits have been integrated by structuring processes, for instance dynamic write/read memories including corresponding cover layers and isolation layers as well as corresponding contact tracks and terminal connections. The semiconductor component typically has a multi-layer structure formed of layers of different materials. The pad and the edge strip can be inventively deposited as the final metallization layer.
The advantage of the invention is that misalignments and deformations of contact elements can be detected before a pad is damaged, by a semi-interactive correction process. At the same time, a secondary advantage is the prevention of secondary harm that occurs when damage is not detected early or as early as possible.
In a preferred embodiment of the inventive semiconductor component, a trench is provided between the pad and the edge strip in order to isolate the pad and the edge strip. This development makes possible a simple and thus cost-effective production.
The edge strip preferably contains a terminal for evaluation logic for detecting an electrical short. A short can be detected by applying a test pin on both the contact strip and the pad. Suitable measures for repositioning the test pin can be initiated directly by the evaluation logic.
When the edge strip surrounds the pad equidistantly, such mispositioning can be detected along the entire perimeter of the pad.
A preferred segmenting of the edge strip has the added advantage that the position of a misalignment of a contact element can be precisely determined from the location of a short and can therefore be precisely corrected.
In accordance with an added feature of the invention, an electrically isolating intermediate layer is disposed between the pad and the electrically conductive edge strip.
According to the invention, the pad can also be part of a test structure. The test structure can also be integrated in the semiconductor device. It is also imaginable for the evaluation logic to be integrated in the semiconductor device at least to the greatest possible extent.
In a particularly preferred embodiment, the contact element is a test pin and/or a connecting wire. The test pin can be placed on the pad for a functionality test. But the pad can also be configured so that a connecting wire that is constructed as a bond wire is connected to it. The quality of the bond connections can thereby be tested with the inventive contact configuration by the evaluating logic.
In the inventive method for forming a contact from an electrically conductive material on a semiconductor material that is provided with at least one integrated circuit, the contact is generated such that it is suitable for the application of a contact element. The contact is so deposited on the semiconductor material as a two-piece contact with a pad and an adjoining edge strip formed of an electrically conductive material, respectively, that the two contact portions are electrically isolated from one another. The edge strip is preferably deposited surrounding the inner contact portion. That leads to the advantageous aligning of the masks or mask structures that are required to the deposition.
Particular advantage is gained by the incorporation of a trench into a layer bearing the two contact portions between the pad and the edge strip. The advantage of the inventive technique is that the two contact portions can then be applied in one processing step by deposition or evaporation coating.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an electrical component with a contact and a method for forming a contact on a semiconductor material, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.